1. Field of the Invention
The present invention relates to a controller for power devices and, more particularly, to a controller for power devices employing high-breakdown-voltage semiconductor elements.
2. Description of the Background Art
FIG. 26 is a circuit diagram of a drive circuit for an AC input three-phase motor which is an example of background art controllers for power devices employing high-breakdown-voltage semiconductor elements. As shown in FIG. 26, an AC three-phase power supply APW serving as a power supply for an AC input three-phase motor M is connected to a converter circuit CC1 between lines P and N, and the respective phases of the AC input three-phase motor M are connected to inverter circuits I1, I2, I3 for controlling the phases, respectively.
The inverter circuit I1 (12, 13) includes a pair of transistors Q1 and Q2 (Q3 and Q4; Q5 and Q6) which are power devices, such as IGBTs (insulated gate bipolar transistors), totem-pole connected between the lines P and N, and a control block SB1 (SB2, SB3). Inputs of the respective phases of the motor M are connected to connection points U, V, W of the totem-pole connected transistors, respectively. Free-wheeling diodes D1 to D6 are connected in inverse-parallel with the transistors Q1 to Q6, respectively. Between the lines P and N are connected a smoothing capacitor C and a brake circuit BK for use in applying electrical brakes to the AC input three-phase motor M and including a diode D7 and a transistor Q7 connected in series. A brake resistor BR exteriorly attached is connected in parallel with the diode D7 in the brake circuit BK. A control block SB4 is connected to the gate electrode of the transistor Q7.
The control blocks SB1, SB2, SB3 forming the inverter circuits I1, I2, I3 and the control block SB4 are connected to an external controller 6 employing a microcomputer and the like. A DC power supply DPW for operating the control blocks SB1, SB2, SB3 is a power supply receiving a single-phase output from the AC three-phase power supply APW. The single-phase output from the AC three-phase power supply APW is connected to primary coils of an isolation transformer TR through a converter circuit CC2. Two DC outputs from secondary coils of the isolation transformer TR are applied to the control blocks SB1, SB2, SB3 through converter circuits. For instance, DC outputs X and Y are applied to the inverter circuit I1.
The arrangement of the control block SB1 of the inverter circuit I1 is shown in FIG. 27. Referring to FIG. 27, control circuits LS1 and LS2 employing LVICs (low-voltage ICs) are connected to the gate electrodes of the transistors Q1 and Q2, respectively. Insulation circuits Z1 and Z2 are connected to the control circuits LS1 and LS2, respectively. Reference potentials G1 and G2 for the control circuits LS1 and LS2 are based on different potentials.
Operation will be discussed with reference to FIGS. 26 and 27. Referring to FIG. 26, the converter circuit CC1 converts a 400 V AC input voltage to a voltage of about 600 V DC which is applied between the lines P and N. Then the smoothing capacitor C between the lines P and N is charged, and ripple on the power supply line is suppressed. The voltage of about 600 V DC is provided as main power supplies for the inverter circuits I1, I2, I3.
Referring to FIG. 27, since the connection point U serving as an output of the inverter circuit I1 is provided between the totem-pole connected transistors Q1 and Q2, the reference potential G1 for the control circuit LS1 is, for example, the 600 V main power supply voltage when the transistor Q1 is ON. In such a construction, a voltage as high as 600 V is applied to the control circuit LS1 if the reference potential G1 for the control circuit LS1 is a ground potential of 0 V.
The LVIC forming the control circuit LS1 normally has an operating voltage of not more than 30 V and is not constructed to withstand the voltage as high as 600 V. Hence, the control circuit LS1 is designed such that the reference potential G1 for the control circuit LS1 is held floating from the ground potential and the main power supply voltage of 600 V becomes the reference potential G1 when the transistor Q1 is ON. A portion in which the main power supply potential is the reference potential is referred to hereinafter as a high potential portion, and a portion in which the ground potential is the reference potential, such as the control circuit LS2, as a low potential portion. It should be noted that the control circuit LS2 in the low potential portion is held floating in the same manner as the control circuit LS1.
To that end, the DC power supplies X and Y insulated through the isolation transformer TR and then rectified by the converter circuit are applied to the control circuits LS1 and LS2 for driving thereof. Further, a control signal from the external controller 6 is applied to the control circuits LS1 and LS2 through the insulation circuits Z1 and Z2 including insulating means such as photocouplers. The DC power supplies X and Y are fed to drive the insulation circuits Z1, Z2 and the control circuits LS1, LS2.
Each of the inverter circuits 12 and 13 includes circuits similar to the insulation circuits Z1, Z2 and the control circuits LS1, LS2 and requires power supplies similar to the DC power supplies X and Y. The drive circuit for the AC input three-phase motor requires at least four DC power supplies since separate DC power supplies are connected respectively to the control circuits in the high potential portions such as the control circuit LS1 and a DC power supply is commonly connected to the control circuits in the low potential portions similar to the control circuit LS2.
The brake circuit BK applies electrical brakes to the motor M which tends to keep rotating after receiving a stop signal from the external controller 6. The circuit arrangement of the control block SB4 for controlling the transistor Q7 is similar to that of the circuits for controlling the low potential transistors in the control blocks SB1 to SB3, and is connected to the external controller 6.
The inverter circuits I1, I2, I3 are well known in the art, and the description of the detailed circuit arrangements thereof will be omitted herein.
As above stated, the conventional controller for the power devices has required particular insulating elements such as photocouplers for insulation of the control signal. In particular, insulation of high-frequency noises has necessitated an advanced insulation technique and costly insulating elements.
The control signal is given from the external controller 6 through the insulating means, resulting in the power devices being less responsive to the control signal and being difficult to integrate.
Further, it has been necessary to individually apply the drive power supply to the control circuits positioned in the high and low potential portions through the isolation transformer TR, which causes an increased size of the power supply portion and a large amount of power consumption. The need for the particular insulating elements, such as photocouplers, as insulating means results in an increased size of a module (Intelligent Power Module; referred to as an IPM hereinafter) designed such that an integrated controller for power devices including a protective circuit, the power devices, and a control power supply are encapsulated in a single package.
For a power device including in-series connected first and second semiconductor circuits between first and second main power supply potentials, the conduction of at least the first semiconductor circuit being controllable by a control signal, the first and second semiconductor circuits providing an output at their connection node, the present invention is intended for a controller for controlling the power device in response to an input signal generated based on the second main power supply potential. According to the present invention, the controller comprises: first signal generator means for generating a first signal in response to the input signal; level shift means for level-shifting the first signal toward the first main power supply potential to produce a second signal; and control signal generator means for generating the control signal for the first semiconductor circuit in response to the second signal, wherein the level shift means includes at least one level shifting semiconductor element between the first and second main power supply potentials and controlled by the first signal, the at least one level shifting semiconductor element having a breakdown voltage characteristic which is not less than a voltage between the first and second main power supply potentials.
According to the controller of the present invention, the first semiconductor circuit is controlled by the input signal generated on the basis of the second main power supply potential through the level shift means including at least one level shifting semiconductor element between the first and second main power supply potentials and controlled by the first signal and having the breakdown voltage characteristic which is not less than the voltage between the first and second main power supply potentials. This increases the responsiveness of the power device to the control signal and improves the integration.
Preferably, the first signal generator means includes pulse generator means for generating a pulse in response to level transition of the input signal to use the pulse as the first signal; the second signal is a shifted pulse obtained by level-shifting the pulse by the level shift means; and the control signal generator means includes latch means for latching the shifted pulse as the first signal to generate the control signal for the first semiconductor circuit.
The pulse responsive to the level transition of the input signal is level-shifted to provide the shifted pulse which acts as the control signal for the first semiconductor circuit. The first signal generator means, the level shift means, and the control signal generator means are simple in construction.
Preferably, the pulse generator means is means for generating first and second pulses in response to positive and negative level transitions of the input signal, respectively, to use the first and second pulses as the first signal; the level shift means includes first and second level shifting semiconductor elements provided between the first and second main power supply potentials and having a breakdown voltage characteristic which is not less than a voltage between the first and second main power supply potentials, the first and second level shifting semiconductor elements level-shifting the first and second pulses toward the first main power supply potential to generate first and second shifted pulses, thereby to provide the second signal; and the latch means latches the second signal including the first and second shifted pulses to use the second signal as the control signal for the first semiconductor circuit.
The first and second pulses responsive to the positive and negative level transitions of the input signal are level-shifted to produce the first and second shifted pulses which act as the control signal for the first semiconductor circuit. With the input signal applied over a long period of time, the level shifting semiconductor elements are prevented from receiving loads over a long period of time and are thus protected. This permits reduction in power consumption.
Preferably, the controller further comprises first operation abnormality detector means for detecting an abnormal operation in the first semiconductor circuit to generate a first abnormality indication signal having a level based on the first main power supply potential; and the level shift means further includes a third level shifting semiconductor element provided between the first and second main power supply potentials and having a breakdown voltage characteristic which is not less than a voltage between the first and second main power supply potentials, the third level shifting semiconductor element level-shifting the first abnormality indication signal toward the second main power supply potential to produce a second abnormality indication signal; and the second abnormality indication signal is a feedback signal to a circuit for generation of the input signal.
Since the first abnormality indication signal indicative of the abnormal operation in the first semiconductor circuit is level-shifted toward the second power supply potential by the third level shifting semiconductor element and is fed back to the circuit for generation of the input signal, the input signal is controlled to cancel the abnormal operation in the first semiconductor circuit.
Preferably, the first operation abnormality detector means includes abnormality indication signal pulse generator means for generating a pulse in response to level transition of the first abnormality indication signal to use the pulse as a pulse signal for the first abnormality indication signal; the second abnormality indication signal is a shifted pulse obtained by level-shifting the pulse signal for the first abnormality indication signal by the third level shifting semiconductor element; and the level shift means includes feedback signal latch means for latching the shifted pulse as the second abnormality indication signal to generate the feedback signal to the circuit for generation of the input signal.
The first abnormality indication signal indicative of the abnormal operation in the first semiconductor circuit is converted into the pulse signal, which is level-shifted toward the second main power supply potential by the third level shifting semiconductor element. The level-shifted signal is applied to the circuit for generation of the input signal as the feedback signal by the feedback signal latch means. This provides the more practical controller for canceling the abnormal operation in the first semiconductor circuit.
Preferably, a first controllable semiconductor element included in the first semiconductor circuit and the first and second level shifting semiconductor elements are of a first conductivity type; and the third level shifting semiconductor element is of a second conductivity type.
The level shift from the second main power supply potential to the first main power supply potential and the level shift from the first main power supply potential to the second main power supply potential are performed without hindrance. The practical circuit arrangement is achieved.
Preferably, the control signal for the first controllable semiconductor element is a first control signal; the control signal generator means is first control signal generator means; the second semiconductor circuit includes a second controllable semiconductor element, the conduction of which is controllable by a second control signal; and the controller further comprises second control signal generator means for generating the second control signal in response to the input signal.
The conduction of the second semiconductor circuit is also controllable. This meets the requirement for the controller to control both the first and second semiconductor circuits.
According to another aspect of the present invention, for a power device including in-series connected first and second semiconductor circuits between first and second main power supply potentials, the conduction of the first and second semiconductor circuits being controllable by first and second control signals, respectively, the first and second semiconductor circuits providing an output at their connection node, a controller for generating the first and second control signals in response to an input signal generated based on the second main power supply potential, the controller comprises: at least one semiconductor element having a breakdown voltage characteristic which is not less than a voltage between the first and second main power supply potentials for generating the first control signal in response to the input signal and for separating potential levels of the first and second control signals from each other.
Since the first semiconductor circuit is controlled by the input signal generated on the basis of the second main power supply potential, the responsiveness of the power device to the control signal is increased, and the integration is improved.
Preferably, the controller further comprises: a current detecting resistor between an electrode of the second controllable semiconductor element which outputs a main current and the second main power supply potential for detecting and converting the main current flowing through the second controllable semiconductor element into a voltage signal corresponding to the main current; and analog signal output means receiving the voltage signal corresponding to the main current for feeding back a value of the main current indicated by the voltage signal to the second control signal generator means in the form of an analog signal.
The main current for the second controllable semiconductor element is converted into the voltage signal, and the analog signal output means feeds back the value of the main current indicated by the voltage signal to the second control signal generator means as the analog signal. The operation of the second controllable semiconductor element is sensed in real time, and the analog signal output means is readily modularized. This permits size reduction of the device.
Preferably, the analog signal output means includes: delay signal generator means for causing the second control signal to delay to generate a delay signal; a gate element having an input and an output and receiving the voltage signal at the input for opening and closing a transmission path of the voltage signal from the input to the output in response to the delay signal; and a capacitor between the output of the gate element and the second main power supply potential, and the analog signal is provided at the output.
This provides the more practical analog signal output means.
Preferably, the controller further comprises: second operation abnormality detector means for detecting an abnormal operation in the second semiconductor circuit to generate a third abnormality indication signal having a level based on the second main power supply potential; and abnormality indication signal identifying means for identifying the second and third abnormality indication signals to feed back a result of the identification to the circuit for generation of the input signal.
The abnormal conditions in the first and second controllable semiconductor elements can be identified, and these means are readily modularized. This permits size reduction of the device.
Preferably, the controller further comprises: input interlock means for detecting timings of generation of the first and second control signals to prevent the first and second control signals from being outputted simultaneously.
The disadvantage due to simultaneous operation of the first and second controllable semiconductor elements is prevented.
Preferably, the controller further comprises: PWM signal generator means for generating first and second PWM signals in response to the input signal, the first and second control signals being generated in response to the first and second PWM signals, respectively.
This allows generation of a signal pattern which turns ON one of the first and second controllable semiconductor elements.
Preferably, the controller is integrated on a single or a plurality of semiconductor substrates and is driven by a single operation power supply for feeding a voltage between the first and second main power supply potentials.
Size reduction of the device is accomplished.
The present invention is also intended for a drive controller for a motor. According to the present invention, the drive controller comprises: in-series connected first and second semiconductor circuits between first and second main power supply potentials; a controller for a power device as recited above; a brake circuit in parallel with the first and second semiconductor circuits for applying an electrical brake to the motor in response to a predetermined stop signal; and a converter circuit for rectifying an AC power supply to provide the first and second main power supply potentials, the first and second semiconductor circuits, the controller, the brake circuit, and the converter circuit being provided in the form of a module.
The motor drive controller is achieved which is reduced in size and has a good responsiveness of the motor to the control signal.
Preferably, the module includes an active filter circuit for increasing a power rate of the drive controller.
There is no need to provide the active filter circuit on the outside of the device. In addition, the motor drive controller is reduced in size.
Preferably, the module includes a power supply circuit for supplying power for the controller recited above from the AC power supply.
The size-reduced motor drive controller is accomplished.
Preferably, the drive controller further comprises: a charge pump circuit between the power supply circuit and a connection point of the first and second semiconductor circuits, the charge pump circuit including a first diode and a capacitor connected in series in order from a positive output of the power supply circuit; and a second diode between the first diode and a control electrode of the first controllable semiconductor element of the first semiconductor circuit, the second diode having a negative electrode connected to a negative electrode of the first diode.
The provision of the second diode in the charge pump circuit prevents the potential at the control electrode of the first controllable semiconductor element of the first semiconductor circuit from increasing due to electrical induction generated during the operation of the second semiconductor circuit. This prevents simultaneous operation of the first and second semiconductor circuits and, accordingly, prevents a short circuit between the first and second power supply potentials.
It is therefore a primary object of the present invention to provide controller for a power device which requires no particular elements for individually insulating high and low potential portions and no insulated power supplies.
It is another object of the invention to provide a drive controller for a motor which employs the controller of the power device and which is modularized.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.